The present invention generally relates to a method for fabricating memory, and more particularly, to a method for fabricating a nonvolatile memory cell with optimum bias condition.
Since the rapid developments of the semiconductor techniques and widespread application of information products, semiconductor devices play an important role, specifically in the flash memory. This memory has excellent program/erase characteristics and has been a master stream in the nonvolatile memory field. However, taken account of transistor integrity, power consumption, threshold voltage level, and noise reduction thereof, the flash memory generally won""t be exactly programmed or erased in the period of data access.
Referring to FIG. 1, the cross-sectional views of the conventional nitride read only memory (NROM), including a nitride layer, as described in U.S. Pat. No. 5,966,603 to Eitan. The nonvolatile memory cell includes an oxide-nitride-oxide (ONO) structure 110, a drain 102 and a gate 112, wherein the ONO structure 110 is composed of a first oxide layer 104, a nitride layer 106 and a second oxide layer 108. In a programming period, a high voltage is put on drain 102 and gate 112 respectively to generate a large amount of electron-hole pairs. Subsequently, several electrons are attracted toward gate 112 by an electrical field in order to be penetrated through the first oxide layer 104 and trapped in the nitride layer 106 for inducing high threshold voltage. In the erasing period, a portion of electrons are removed away from the nitride layer 106, or a portion of holes are injected into nitride layer 106 to be neutralized with the portion of electrons, and hence the remaining electrons part with other portion of holes within the nitride layer 106. As a whole, such neutralization may bring about lower threshold voltage which is defined as minimum gate voltage in response to activating current, typically of 1 xcexcA, between the source and drain 102.
If the voltage between the drain 102 and gate 112 is not an optimum bias condition, the electric field might vary from the electrons-injected so that an erasing result occurs as a programming action is performed.
Another reference is titled xe2x80x9cA true single-transistor oxide-nitride-oxide EEPROM device,xe2x80x9d by T. Y. Chan, K. K. Young, and Chenming Hu in IEEE EDL-8, No. 3 pp93-95, March 1987. A floating gate is replaced with ONO structure that hot-electrons are used to change the threshold voltage thereof Similarly, if the voltage between the drain 102 and gate 112 is not an optimum bias condition, the electric field might vary from the electrons-injected so that an erasing result occurs as a programming action is performed. For data accessing, such action disagreement will result in data errors or data being lost.
In view of the problems encountered with the foregoing conventional nonvolatile memory cell, if bias condition of drain/gate of the memory cell is not an optimum value, the expected writing operation of the memory cell may be misused, or the data is wiped out.
As a result, the primary object of the present invention is, after nonvolatile memory cell is made, to provide an optimum bias condition of drain/gate in response to programming or erasing operation, thereby preventing the nonvolatile memory cell from encountering data errors.
Another object of the present invention is, during the fabrication period of the nonvolatile memory cell, in advance, to provide an optimum bias condition in drain/gate to enable a better program operation in the nonvolatile memory cell.
According to the above objects, the present invention sets forth a method of forming an optimum bias condition of the nonvolatile memory cell.
Initially, an ONO structure is formed on substrate wherein the ONO structure has a first oxide layer, a nitride layer and a second oxide layer. Afterwards, a plurality of openings is formed on the ONO structure and a portion of substrate is exposed. An optimum condition of a nonvolatile memory cell having a threshold voltage region wherein the threshold voltage region can be optimum by adjusting a lateral electric field between a drain and a gate to transfer a plurality of electrons into the ONO structure. Thereafter, an implant process is performed to form a plurality of bit lines on substrate. An oxide layer is formed on bit lines to create a bit lines oxide layer. Finally, a polysilicon is formed on bit lines oxide layer and the ONO structure to produce the nonvolatile memory cell. Alternatively, after nonvolatile memory cell is made, the optimum threshold voltage region can be selected by adjusting a lateral electric field between a drain and a gate to transfer a plurality of electrons into the ONO structure. In other words, electrons are injected into the nitride layer in responsive to the expected writing effect.
In summary, the present invention provides a method of forming a nonvolatile memory cell with optimum bias condition by adjusting a voltage between drain and gate. A similar erased region, a second region, can be avoided, but a third region is formed with efficiency. Moreover, the voltage of drain/gate is properly designed to acquire an optimum bias condition such that the nonvolatile memory cell has a correct writing operation.